LCD Panel Timing Controller - Myson Century
Description
GENERAL DESCRIPTION
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The CS5843 is a TFT-LCD timing controller, which is applicable to 6-bit data XGA (1024*768), SXGA (1280*1024).
CS5843 can update the response timing for display mode of XGA and SXGA automatically.
CS5843 provides a selectable polarity check function to inverse output data for EMI reducing, when the toggle number of ODD/EVEN RGB outputs is larger than 10.
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LCD U Panel Timing Controller (15")
FEATURES (continued) • Correspondent to control timing & specific resolution for different Driver IC by changing a Mask: 1.
can vary the pulse width & starting position of LP signal and POL signal polarity position changed along with LP signal 2.
can vary the pulse width & starting position of CLKV signal and tgs time • Control ASIC output timing design is based on Data Enable signals • Embedded Power On Reset circuits, Vth=2.
1V, tolerance ± 0.
3V • ESD spec.
4KV • Power On Latch Up 200mA/6.
6V • Single 3.
3V supply • 144-pin LQFP package
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CS5843
BLOCK DIAGRAM
DENA VD
3U HOL PL QD U\
POWER ON RESET
FEATURES • CS5843 Interface (5V/3.
3V[CMOS] input, 3.
3V[CMOS] output) • Single (XGA2: 65MHz)/dual (XGA: 32.
5MHz) 6-bit Data input; dual port 6-bit output; SXGA auto detective • Timing adjustable for horizontal clock output
HD DCLK1 INV PNDCLK PNVD PNHD POLIN ICMD(2~1) DATAHT SXMD
PNHMS PLMD SCMD SET HITAENB CLKHT
GT(2~1) ODDRI(5~0) ODDGI(5~0) ODDBI(5~0) EVENRI(5~0) EVENGI(5~0) EVENBI(5~0)
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STH1/STH8 GENERATOR
POL/SHC GENERATOR
CLKV GENERATOR
STV1/STV3 GENERATOR
LP GENERATOR
CLKH GENERATOR
CLKV STV1 STV2 CLKH STH1 STH8 LP POL SHC RLSC
ODDGO(5~0) EVENGO(5~0) ODDRO(5~0) EVENRO(5~0) ODDBO(5~0) EVENBO(5~0) HMS1 HMS2
DATA-PATH
DELAY
OUTPUT SELECTOR INPUT SELECTOR SAMPLE POLARITY
RGBD
CS5843
Myson Century, Inc.
Taiwan: No.
2, Industry East Rd.
III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 1485 Saratoga Ave.
#200 San ...
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