N-Channel MOSFET - Fairchild
Description
August 1996
NDT014L N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.
This very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes.
Thesedevices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed.
Features
2.
8 A, 60 V.
RDS(ON) = 0.
2 Ω @ VGS = 4.
5 V RDS(ON) = 0.
16 Ω @ VGS = 10 V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used surface mount package.
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D
D
G
D
S
G
S
Absolute Maximum Ratings
Symbol VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current
T A = 25°C unless otherwise noted
NDT014L 60 ± 20
(Note 1a)
Units V V A
- Continuous - Pulsed
± 2.
8 ± 10
PD
Maximum Power Dissipation
(Note 1a) (Note 1b) (Note 1c)
3 1.
3 1.
1 -65 to 150
W
TJ,TSTG
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
42 12
°C/W °C/W
© 1997 Fairchild Semiconductor Corporation
NDT014L Rev.
D
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 60 V, VGS = 0 V TJ = 55°C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 µA TJ = 125°C Static Drain-Source On-Resi...
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