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M74HC165

ST Microelectronics
Part Number M74HC165
Manufacturer ST Microelectronics
Description 8-bit PISO shift register
Published May 6, 2005
Detailed Description M74HC165 8 BIT PISO SHIFT REGISTER s s s s s s s HIGH SPEED : tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION...
Datasheet PDF File M74HC165 PDF File

M74HC165
M74HC165

Overview
M74HC165 8 BIT PISO SHIFT REGISTER s s s s s s s HIGH SPEED : tPD = 15ns (TYP.
) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.
) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.
) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 165 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC165B1R M74HC165M1R T&R M74HC165RM13TR M74HC165TTR DESCRIPTION The M74HC165 is an high speed CMOS 8 BIT PISO SHIFT REGISTER fabricated with silicon gate C2MOS technology.
This device contains eight clocked master slave RS flip-flops connected as a shift register, with auxiliary gating to provide over-riding asynchronous parallel entry.
Parallel data enters when the shift/load input is low.
The parallel data can change while shift/load is low, provided that the recommended set-up and hold times are observed.
For clocked operation, shift/load must be high.
The two clock input perform identically; one can be used as a clock inhibit by applying a high signal; to permit this operation clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the same response as rising clock edge.
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 M74HC165 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 7 9 SYMBOL NAME AND FUNCTION 10 11, 12, 13, A to H 14, 3, 4, 5, 6 15 CLOCK INH 8 GND 16 Vcc SHIFT/LOAD Data Inputs Complementary Output QH QH Serial Output Clock Input (LOW to CLOCK HIGH, Edge Triggered SI Serial Data Inputs Parallel Data Inputs Clock Inhibit Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS SHIFT / LOAD L H H H H H H X H CLOCK INH X L L L L H X CLOCK X SI ...


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