M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output d.
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and data mask are referenced to both edges of DQS - 4 bank operations are controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge is controlled by A10 - 8192.
Similar Product
No. | Part # | Manufacture | Description | Datasheet |
---|---|---|---|---|
1 | M2S12D30TP-75 |
Mitsubishi |
512M Double Data Rate Synchronous DRAM | |
2 | M2S12D30TP-10 |
Mitsubishi |
512M Double Data Rate Synchronous DRAM | |
3 | M2S12D30TP-10L |
Mitsubishi |
512M Double Data Rate Synchronous DRAM | |
4 | M2S12D30TP |
Mitsubishi |
512M Double Data Rate Synchronous DRAM | |
5 | M2S12D20TP |
Mitsubishi |
512M Double Data Rate Synchronous DRAM |