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M5M4V64S20ATP-10

Part Number	M5M4V64S20ATP-10
Manufacturer	Mitsubishi
Description	64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Published	Apr 26, 2005
Detailed Description	SDRAM (Rev.0.2) Jan'97 Preliminary MITSUBISHI LSIs M5M4V64S20ATP-8, -10, -12 64M (4-BANK x 4194304-WORD x 4-BIT) Sync...
Datasheet	M5M4V64S20ATP-10 PDF File

Overview

SDRAM (Rev.
0.
2) Jan'97 Preliminary MITSUBISHI LSIs M5M4V64S20ATP-8, -10, -12 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.
DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface.
All inputs and outputs are referenced to the rising edge of CLK.
The M5M4V64S20ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC (Vref) DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss FEATURES - Single 3.
3v±0.
3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A9 - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.
8mm lead pitch Max.
Frequency M5M4V64S20ATP-8 M5M4V64S20ATP-10 M5M4V64S20ATP-12 125MHz 100MHz 83MHz CLK Access Time 6ns 8ns 8ns CLK CKE /CS /RAS /CAS /WE DQ0-3 DQM A0-11 BA0,1 Vdd VddQ Vss VssQ : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output 400mil 54pin TSOP(II) MITSUBISHI ELECTRIC 1 SDRAM (Rev.
0.
2) Jan'97 Pre...

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