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QL2009-1PB256I

Part Number	QL2009-1PB256I
Manufacturer	ETC
Description	3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
Published	Apr 16, 2005
Detailed Description	3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev. C pASIC 2 HIGHLIGHTS ® QL2009 Ulti...
Datasheet	QL2009-1PB256I PDF File

Overview

3.
3V and 5.
0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.
C pASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 9,000 usable ASIC gates, 225 I/O pins -16-bit counter speeds exceeding 200 MHz -9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os -3-layer metal ViaLink® process for small die sizes -100% routable and pin-out maintainable 3 pASIC 2 Advanced Logic Cell and I/O Capabilities -Complex functions (up to 16 inputs) in a single logic cell -High synthesis gate utilization from logic cell fragments -Full IEEE Standard JTAG boundary scan capability -Individually-controlled input/feedback registers and OEs on all I/O pins Other Important Family Features -3.
3V and 5.
0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.
0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The QL2009 is a 9,000 usable ASIC gate,16,000 usable PLD gate member of the pASIC 2 family of FPGAs.
pASIC 2 FPGAs employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices.
The flexibility and speed make pASIC 2 devices an efficient and high performance silicon solution for designs described using HDLs such as Verilog and VHDL, as well as schematics.
The QL2009 contains 672 logic cells.
With 225 maximum I/Os, the QL2009 is available in 144-pin TQFP, 208-PQFP, and 256-pin PBGA packages.
Software support for the complete pASIC families, including the QL2009, is available through three basic packages.
The turnkey QuickWorks® package ...

Similar Datasheet

QL2009-1PB256C 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility - ETC
QL2009-1PB256I 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility - ETC

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