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K4S281632C-TC1H

Part Number	K4S281632C-TC1H
Manufacturer	Samsung semiconductor
Description	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Published	Apr 7, 2005
Detailed Description	K4S281632C CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Mar. 2000 * Samsung Ele...
Datasheet	K4S281632C-TC1H PDF File

Overview

K4S281632C CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.
0 Mar.
2000 * Samsung Electronics reserves the right to change products or specification without notice.
Rev.
0.
0 Mar.
2000 K4S281632C Revision History Revision 0.
0 (March 21, 2000) • Changed tOH of K4S280432C-TC75/TL75 from 2.
7ns to 3.
0ns.
• Deleted -10 and -80 speed specification.
CMOS SDRAM Rev.
0.
0 Mar.
2000 K4S281632C 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.
3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -.
CAS latency (2 & 3) -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) Part No.
K4S281632C-TC/L75 K4S281632C-TC/L1H K4S281632C-TC/L1L CMOS SDRAM GENERAL DESCRIPTION The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION Max Freq.
133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL Interface Package 54 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 2M x 16 Sense AMP 2M x 16 2M x 16 2M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col.
Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UD...

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