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IDT71V3558S

Integrated Device Technology
Part Number IDT71V3558S
Manufacturer Integrated Device Technology
Description 3.3V Synchronous ZBT SRAMs
Published Apr 5, 2005
Detailed Description 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs x x IDT71V3556S IDT71V3558S I...
Datasheet PDF File IDT71V3558S PDF File

IDT71V3558S
IDT71V3558S


Overview
128K x 36, 256K x 18 3.
3V Synchronous ZBT SRAMs 3.
3V I/O, Burst Counter Pipelined Outputs x x IDT71V3556S IDT71V3558S IDT71V3556SA IDT71V3558SA Features 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.
2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW 1 - BW4) control (May tie active) Three chip enables for simple depth expansion 3.
3V power supply (±5%), 3.
3V I/O Supply (VDDQ) Optional- Boundary Scan JTAG Interface (IEEE 1149.
1 compliant) Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) Description The IDT71V3556/58 are 3.
3V high-speed 4,718,592-bit (4.
5 Megabit) synchronous SRAMS.
They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.
Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.
The IDT71V3556/58 contain data I/O, address and control signal registers.
Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 to be suspended as long as necessary.
All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired.
If any one of these three are not asserted when ADV/LD is low, no new memory operation can...


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