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HYB25D256800BT

Part Number	HYB25D256800BT
Manufacturer	Infineon Technologies AG
Description	256MBit Double Data Rata SDRAM
Published	Apr 3, 2005
Detailed Description	HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9 Fe...
Datasheet	HYB25D256800BT PDF File

Overview

HYB25D256[800/160]BT(L)-[5/5A] 256MBit Double Data Rata SDRAM Preliminary DDR400 Data Sheet Addendum Jan.
2003, V0.
9 Features CAS Latency and Clock Frequency CAS Latency 2 2.
5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200 • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is center-aligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK tran...

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