2.5V/3.3V ALVT 16-bit transceiver - NXP
Description
INTEGRATED CIRCUITS
74ALVT162245 2.
5V/3.
3V ALVT 16-bit transceiver with 30W termination resistors (3-State)
Product specification Supersedes data of 1996 Mar 05 IC23 Data Handbook 1998 Feb 13
Philips Semiconductors
Philips Semiconductors
Product specification
2.
5V/3.
3V 16-bit transceiver with 30Ω termination resistors (3-State)
74ALVT162245
FEATURES
• 16-bit bidirectional bus interface • 3-State buffers • 5V I/O compatibile • Output capability: +12mA/-12mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction permitted • Outputs include series resistance of 30Ω making external • Power-up 3-State • No bus current loading when output is tied to 5V bus • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model termination resistors unnecessary resistors to hold unused inputs
DESCRIPTION
The 74ALVT162245 is a high-performance BiCMOS product designed for VCC operation at 2.
5V or 3.
3V with I/O compatibility up to 5V.
This device is a 16-bit transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions.
The control function implementation minimizes external timing requirements.
The device features an Output Enable (nOE) input for easy cascading and a Direction (DIR) input for direction control.
The 74ALVT162245 is designed with 30Ω series resistance in both the High and Low states of the output.
This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O ICCZ PARAMETER Propagation delay nAx to nBx or nBx to nAx Input capacitance DIR, OE I/O pin capacitance Total supply current CL = 50pF VI = 0V or VCC VI/O = 0V or VCC Outputs disabled CONDITIONS Tamb = 25°C TYPICAL 2.
5V 2.
9 2.
4 3 9 40 3.
3V 2.
...
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