Quad 2-input NAND gate - NXP
Description
INTEGRATED CIRCUITS
DATA SHEET
74AHC00; 74AHCT00 Quad 2-input NAND gate
Product specification Supersedes data of 1998 Dec 09 File under Integrated Circuits, IC06 1999 Sep 23
Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C.
DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
The 74AHC/AHCT00 provides the 2-input NAND function.
CI CO CPD Note 1.
H = HIGH voltage level; L = LOW voltage level.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.
0 ns.
FUNCTION TABLE See note 1.
INPUT nA L L H H nB L H L H
74AHC00; 74AHCT00
OUTPUT nY H H H L
TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.
2 AHCT 3.
3 3.
0 4.
0 7.
0 ns pF pF pF UNIT
VI = VCC or GND 3.
0 4.
0 7.
0
Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts.
2.
The condition is VI = GND to VCC.
PINNING PIN 1, 4, 9 and 12 2, 5, 10 and 13 3, 6, 8 and 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC DESCRIPTION data inputs data inputs data outputs ground (0 V) DC supply voltage
1999 Sep 23
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate
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