Octal D-Type Flip-Flop - STMicroelectronics
Description
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74ACT574
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
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HIGH SPEED: fMAX = 250 MHz (TYP.
) at VCC = 3.
3V LOW POWER DISSIPATION: ICC = 8 µA (MAX.
) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.
8V (MAX) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 4.
5V to 5.
5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY
DIP
PACKAGE DIP SOP TSSOP
SOP
ORDER CODES T UBE M74ACT574B M74ACT574M
TSSOP
T& R M74ACT574MTR M74ACT574TTR
DESCRIPTION The ACT574 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q outputs will be set to logic state that were setup at the D inputs.
PIN CONNECTION AND IEC LOGIC SYMBOLS
While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
The output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off.
The device is designed to interface directly High Speed CMOS system with TTL and NMOS components.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
February 2000
1/11
74ACT574
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND FUNCT ION 3 State Output Enable Input (Active LOW) Data Inputs
Q0 to Q7
3 State Outputs
CLOCK GND VCC
Clock Input (LOW to HIGH, edge triggere...
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