TRI-STATE Quad Registers - National Semiconductor
Description
54173 DM54173 DM74173 TRI-STATE Quad D Registers
June 1989
54173 DM54173 DM74173 TRI-STATE Quad D Registers
General Description
These four-bit registers contain D-type flip-flops with totempole TRI-STATE outputs capable of driving highly capacitive or low-impedance loads The high-impedance state and increased high-logic-level drive provide these flip-flops with the capability of driving the bus lines in a bus-organized system without need for interface or pull-up components Gated enable inputs are provided for controlling the entry of data into the flip-flops When both data-enable inputs are low data at the D inputs are loaded into their respective flipflops on the next positive transition of the buffered clock input Gate output control inputs are also provided When both are low the normal logic states of the four outputs are available for driving the loads or bus lines The outputs are disabled independently from the level of the clock by a high logic level at either output control input The outputs then present a high impedance and neither load nor drive the bus line Detailed operation is given in the function table To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels the output control circuitry is designed so that the average output disable times are shorter than the average output enable times
Features
Y Y
Y
Y Y Y Y Y
TRI-STATE outputs interface directly with system bus Gated output control lines for enabling or disabling the outputs Fully independent clock elminates restrictions for operating in one of two modes Parallel load Do nothing (hold) For application as bus buffer registers Typical propagation delay 18 ns Typical frequency 30 MHz Typical power dissipation 250 mW Alternate Military Aerospace device (54173) is available Contact a National Semiconductor Sales Office Distributor for specifications
Connection Diagram
Dual-In-Line Package
Function Table
Inputs Data Enable Clear H L L L L L Clock G1 X...
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