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HM-6518883

Intersil Corporation
Part Number HM-6518883
Manufacturer Intersil Corporation
Description 1024 x 1 CMOS RAM
Published Mar 26, 2005
Detailed Description HM-6518/883 March 1997 1024 x 1 CMOS RAM Description The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using sel...
Datasheet PDF File HM-6518883 PDF File

HM-6518883
HM-6518883

Overview
HM-6518/883 March 1997 1024 x 1 CMOS RAM Description The HM-6518/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to achieve high performance and low power operation.
On chip latches are provided for address and data outputs allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance state for use in expanded memory arrays.
The HM-6518/883 is a fully static RAM and may be maintained in any state for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over temperature.
Features • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.
2.
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• Low Power Standby .
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50µW Max • Low Power Operation .
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20mW/MHz Max • Fast Access Time.
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180ns Max • Data Retention .
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at 2.
0V Min • TTL Compatible Input/Output • High Output Drive - 2 TTL Loads • High Noise Immunity • On-Chip Address Register • Two-Chip Selects for Easy Array Expansion • Three-State Output Ordering Information PACKAGE CERDIP TEMP.
RANGE -55oC to +125oC PART NUMBER HM1-6518/883 PKG.
NO.
F18.
3 Pinout HM-6518/883 (CERDIP) TOP VIEW S1 E A0 A1 A2 A3 A4 Q GND 1 2 3 4 5 6 7 8 9 18 VCC 17 S2 16 D 15 W 14 A9 13 A8 12 A7 11 A6 10 A5 PIN A E W S D Q DESCRIPTION Address Input Chip Enable Write Enable Chip Select Data Input Data Output CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.
intersil.
com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2986.
1 6-85 HM-6518/883 Functional Diagram A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 G 32 GATED COLUMN DECODER AND DATA I/O D LATCH A L W A E 5 A 5 Q Q GATED ROW DECODER 32 32 x 32 MATRIX D A LATCH...


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