1024 x 1 CMOS RAM - Intersil Corporation
Description
HM-6508/883
March 1997
1024 x 1 CMOS RAM
Description
The HM-6508/883 is a 1024 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to achieve high performance and low power operation.
On chip latches are provided for address allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance state for use in expanded memory arrays.
The HM-6508/883 is a fully static RAM and may be maintained in any state for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over temperature.
Features
• This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.
2.
1.
• Low Power Standby .
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50µW Max • Low Power Operation .
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20mW/MHz Max • Fast Access Time.
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180ns Max • Data Retention .
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0V Min • TTL Compatible Input/Output • High Output Drive - 2 TTL Loads • On-Chip Address Register
Ordering Information
PACKAGE CERDIP TEMP.
RANGE 180ns 250ns PKG.
NO.
F16.
3 -55oC to +125oC HM1HM16508B/883 6508/883
Pinout
HM1-6508/883 (CERDIP) TOP VIEW
E 1 A0 2 A1 3 A2 4 A3 5 A4 6 Q 7 GND 8
16 VCC 15 D 14 W 13 A9 12 A8 11 A7 10 A6 9 A5
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.
intersil.
com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2985.
1
6-69
HM-6508/883 Functional Diagram
A5 A6 A7 A8 A9 A LATCHED ADDRESS REGISTER 5 A 5 32 D A GATED COLUMN DECODER AND DATA I/O 5 A A 5 Q GATED ROW DECODER 32 32 x 32 MATRIX
A
W
E
LATCHED ADDRESS REGISTER
A0 A1 A2 A3 A4
NOTES: 1.
All lines positive logic - active high.
2.
Three-state buffers: A high → output...
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