4096 x 1 CMOS RAM - Intersil Corporation
Description
HM-6504/883
March 1997
4096 x 1 CMOS RAM
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology.
The device utilizes synchronous circuitry to achieve high performance and low power operation.
On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems.
The data output can be forced to a high impedance state for use in expanded memory arrays.
Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors.
The HM-6504/883 is a fully static RAM and may be maintained in any state for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over temperature.
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.
2.
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• Low Power Standby .
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125µW Max • Low Power Operation .
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35mW/MHz Max • Data Retention .
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at 2.
0V Min • TTL Compatible Input/Output • Three-State Output • Standard JEDEC Pinout • Fast Access Time.
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120/200ns Max • 18 Pin Package for High Density • On-Chip Address Register • Gated Inputs - No Pull Up or Pull Down Resistors Required
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 200ns HM1-6504B/883 300ns HM1-6504/883 PKG.
NO F18.
3
Pinout
HM-6504/883 (CERDIP) TOP VIEW
A0 A1 A2 A3 A4 A5 Q W GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 D 10 E
PIN A E W D Q
DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.
intersil.
com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2993.
1
6-134
HM-6504/883 Functional Diagram
LSB A8 A7 A6 A0 A1 A2
A LATCHED ADDRES...
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