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ASM34012C

Apuls Intergrated Circuits
Part Number ASM34012C
Manufacturer Apuls Intergrated Circuits
Description VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
Published Mar 24, 2005
Detailed Description ASM34012C DATA SHEET ASM34012C ASM34012C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Descri...
Datasheet PDF File ASM34012C PDF File

ASM34012C
ASM34012C


Overview
ASM34012C DATA SHEET ASM34012C ASM34012C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.
0 General Description The ASM34012C is very low cost voice synthesizer with 4-bit microprocessor.
It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc.
It consists of 22 instructions in the device.
With CMOS technology and halt function can minimize power dissipation.
Its architecture is similar to RISC, with two stages of instruction pipeline.
It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles).
1.
1 Feature ‹ Single power supply can operate from 2.
4V through 5V ‹ Internal Program ROM: 4K x 10-bit ‹ 1 sets of 20-bit DPR can access up to 1024K x 10 bits data memory space ‹ Data Registers: • 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) • Unbanked special function registers (SFR) range: 20h-3Fh ‹ I/O Ports: • PRA: 4-bit I/O Port A (2Bh) • PRB: 4-bit Output Port B (2Dh) • PRC: 4-bit Input Port C (2Fh) ‹ On-chip clock generator: Resistive Clock Drive(RM) ‹ Timer: 1 ‹ ‹ ‹ ‹ ‹ • Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 1 Rev 1.
2 ASM34012C FIGURE 1.
1 : Block Diagram of ASM34012C Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[19:12]) =00000000b ADDR[19:0] Stack(12) (2-Level) 0 ROM_ADDR[19:0] 1 DPR3,2,1 DPR[19:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder PCLATCH(8) PCH(8) DLATCH(10) ROM_Data[9:0] Data Bus[3:0] Accumlator(4) Instruction Bus [9:0] SRAM ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh Timer0(9) PRA(4) PRB(4) PRC(4) P1,P2,P3,P4 enter test mode ( Voice synthesizer ) Clock Generator Tes...



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