J-FET INPUT LOW-NOISE OPERATIONAL AMPLIFIER - Renesas
Description
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC4071
J-FET INPUT LOW-NOISE OPERATIONAL AMPLIFIER
DESCRIPTION The µPC4071 is a J-FET input operational amplifier.
This product is designed as low noise version of the µPC4081.
The features of the µPC4071 are more improved input equivalent noise voltage, input offset voltage and input bias current than those of µPC4081.
By these features, the µPC4071 is excellent choice for wide variety of applications including audio preamplifier and active filter.
FEATURES • Low noise: en = 18 nV/ Hz (TYP.
) • Very low input bias and offset currents • Output short circuit protection • High input impedance.
.
.
J-FET Input stage • Internal frequency compensation • High slew rate.
.
.
13 V/µs (TYP.
)
ORDERING INFORMATION Part Number µPC4071C µPC4071G2
Package 8-pin plastic DIP (7.
62 mm (300)) 8-pin plastic SOP (5.
72 mm (225))
EQUIVALENT CIRCUIT
R1
Q9
Q5
(2) II
IN (3)
Q1 Q2 Q6
Q8 Q10
R6 C1
Q7
D1
(1) Q3
Q4 (5)
Q11
OFFSET
R2 R3 R4
R5
R7
NULL
OFFSET NULL
Q14 Q12
R8
R9 Q13
R10 Q15
R11
V+ (7)
Q16
OUT (6) D2
V– (4)
PIN CONFIGURATION (Top View)
µPC4071C, 4071G2
OFFSET NULL
1
8 NC
II 2 IN 3
_+
7 V+ 6 OUT
_ V4
OFFSET 5 NULL
Remark NC : No Connection
The information in this document is subject to change without notice.
Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country.
Please check with local NEC representative for availability and additional information.
Document No.
G15204EJ4V0DS00 (4th edition) (Previous No.
IC-1616)
The mark 5 shows major revised points.
©
Date Published November 2000 NS CP(K)
Printed in Japan
1987
µPC4071
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Symbol
Ratings
Unit
Voltage between V+ and V– Note 1
V+ – V–
–0.
3 to +36
V
Differential Input Voltage
VID
Input VoltageNote 2
VI
Output VoltageNote 3
VO
Power Dissipation
C PackageNote 4
PT
G2 PackageNote 5
Output Short Circuit DurationNote 6
±30
...
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