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LMK03200

Part Number	LMK03200
Manufacturer	Texas Instruments
Description	Family Precision 0-Delay Clock Conditioner
Published	Jul 2, 2023
Detailed Description	LMK03200 www.ti.com SNAS478C – JULY 2009 – REVISED APRIL 2013 LMK03200 Family Precision 0-Delay Clock Conditioner wit...
Datasheet	LMK03200 PDF File

Overview

LMK03200 www.
ti.
com SNAS478C – JULY 2009 – REVISED APRIL 2013 LMK03200 Family Precision 0-Delay Clock Conditioner with Integrated VCO Check for Samples: LMK03200 1 Introduction 1.
1 Features 12 • Integrated VCO with Very Low Phase Noise Floor • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz • VCO Divider Values of 2 to 8 (All Divides) – Bypassable with VCO Mux When Not in 0delay Mode • Channel Divider Values of 1, 2 to 510 (Even Divides) • LVDS and LVPECL Clock Outputs • Partially Integrated Loop Filter • Dedicated Divider and Delay Blocks on Each Clock Output • 0-delay Outputs • Internal or External Feedback of Output Clock • Delay Blocks on N and R Phase Detector Inputs for Lead/Lag Global Skew Adjust • Pin Compatible Family of Clocking Devices • 3.
15 to 3.
45 V Operation • Package: 48 Pin WQFN (7.
0 x 7.
0 x 0.
8 mm) • 200 fs RMS Clock Generator Performance (10 Hz to 20 MHz) with a clean input clock 1.
2 Target Applications • Data Converter Clocking • Networking, SONET/SDH, DSLAM • Wireless Infrastructure • Medical • Test and Measurement • Military / Aerospace Device LMK03200 Outputs 3 LVDS 5 LVPECL VCO Tuning Range RMS Jitter (MHz) (fs) 1185 - 1296 800 Recovered ³GLUW\´ FORFN RU clean clock OSCin LMK03200 Family Precision Clock Conditioner Fout > 1 Gsps ADC CLKout0 CLKout1 CLKout4 CLKout7 LMX2531 PLL+VCO Serializer/ Deserializer FPGA DAC 0XOWLSOH ³FOHDQ´ FORFNV DW different frequencies 1.
3 Description The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock.
The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port.
Internally, the VCO output goes through a VCO divider to feed ...

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