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CAT28C65B

ON Semiconductor
Part Number CAT28C65B
Manufacturer ON Semiconductor
Description 64K-Bit CMOS PARALLEL EEPROM
Published Jul 14, 2022
Detailed Description 64K-Bit CMOS PARALLEL EEPROM CAT28C65B FEATURES s Fast read access times: – 90/120/150ns s Low power CMOS dissipation:...
Datasheet PDF File CAT28C65B PDF File

CAT28C65B
CAT28C65B


Overview
64K-Bit CMOS PARALLEL EEPROM CAT28C65B FEATURES s Fast read access times: – 90/120/150ns s Low power CMOS dissipation: – Active: 25 mA max.
– Standby: 100 µA max.
s Simple write operation: – On-chip address and data latches – Self-timed write cycle with auto-clear s Fast write cycle time: – 5ms max s CMOS and TTL compatible I/O s Hardware and software write protection s Commercial, industrial and automotive temperature ranges s Automatic page write operation: – 1 to 32 bytes in 5ms – Page load timer s End of write detection: – Toggle bit – DATA polling – RDY/BUSY s 100,000 program/erase cycles s 100 year data retention DESCRIPTION The CAT28C65B is a fast, low power, 5V-only CMOS parallel EEPROM organized as 8K x 8-bits.
It requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware.
DATA Polling, a RDY/BUSY pin and Toggle status bits signal the start and end of the self-timed write cycle.
Additionally, the CAT28C65B features hardware and software write protection.
The CAT28C65B is manufactured using Catalyst’s advanced CMOS floating gate technology.
It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDECapproved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.
BLOCK DIAGRAM A5–A12 ADDR.
BUFFER & LATCHES VCC CE OE WE INADVERTENT WRITE PROTECTION CONTROL LOGIC A0–A4 RDY/BUSY TIMER ADDR.
BUFFER & LATCHES ROW DECODER HIGH VOLTAGE GENERATOR DATA POLLING, TOGGLE BIT & RDY/BUSY LOGIC COLUMN DECODER 8,192 x 8 EEPROM ARRAY 32 BYTE PAGE REGISTER I/O BUFFERS I/O0–I/O7 © 2009 SCILLC.
All rights reserved.
Characteristics subject to change without notice 1 Doc.
No.
MD-1009, Rev.
H CAT28C65B PIN CONFIGURATION DIP Package (P, L) RDY/BUSY A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 ...


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