OCTAL TRANSPARENT D-TYPE FLIP-FLOPS - Texas Instruments
Description
D Operating Voltage Range of 4.
5 V to 5.
5 V D State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
D Full Parallel Access for Loading
SN54BCT574 .
.
.
J OR W PACKAGE SN74BCT574 .
.
.
DB, DW, N, OR NS PACKAGE
(TOP VIEW)
SN54BCT574, SN74BCT574 OCTAL TRANSPARENT D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS074C − SEPTEMBER 1991 − REVISED MARCH 2003
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)
SN54BCT574 .
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.
FK PACKAGE (TOP VIEW)
1Q
VCC
OE
1D
2D
OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10
20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 CLK
8D
GND
CLK
3 2 1 20 19
3D 4
18 2Q
4D 5
17 3Q
5D 6
16 4Q
6D 7
15 5Q
7D 8
14 6Q
9 10 11 12 13
8Q
7Q
description/ordering information
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads.
They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP − N
Tube
SN74BCT574N
SN7...
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