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GM71CS17403CLJ

Hynix Semiconductor
Part Number GM71CS17403CLJ
Manufacturer Hynix Semiconductor
Description CMOS DRAM
Published Feb 4, 2021
Detailed Description Description The GM71C(S)17403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit. GM71C(S)17403C/CL...
Datasheet PDF File GM71CS17403CLJ PDF File

GM71CS17403CLJ
GM71CS17403CLJ

Overview
Description The GM71C(S)17403C/CL is the new generation dynamic RAM organized 4,194,304 words x 4 bit.
GM71C(S)17403C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology.
The GM71C(S)17403C/CL offers Extended Data Out (EDO) Mode as a high speed access mode.
Multiplexed address inputs permit the GM71C(S)17403C/CL to be packaged in a standard 300 mil 24(26) pin SOJ and a standard 300mil 24(26) pin plastic TSOP II.
The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.
System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
Pin Configuration 24(26) SOJ GM71C(S)17403C/CL 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM Features * 4,194,304 Words x 4 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time (Unit: ns) t t t t RAC CAC RC HPC GM71C(S)17403C/CL-5 50 13 84 20 GM71C(S)17403C/CL-6 60 15 104 25 GM71C(S)17403C/CL-7 70 18 124 30 * Low Power Active : 660/605/550mW (MAX) Standby : 11mW (CMOS level : MAX) : 0.
83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L-version) * Battery Backup Operation (L-version) * Test Function : 16bit parallel test mode 24(26) TSOP II VCC 1 I/O1 2 I/O2 3 WE 4 RAS 5 NC 6 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS 25 I/O4 24 I/O3 23 CAS 22 OE 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS VCC 1 I/O1 2 I/O2 3 WE 4 RAS 5 A11 6 A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26 VSS 25 I/O4 24 I/O3 23 CAS 22 OE 21 A9 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS (Top View) Rev 0.
1 / Apr’01 Pin Description Pin Function Pin A0-A10 Address Inputs WE A0-A10 Refresh Address Inputs OE I/O1-I/O4 Data-input/...


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