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74SSTUB32865A

Texas Instruments

28-BIT TO 56-BIT REGISTERED BUFFER - Texas Instruments


74SSTUB32865A
74SSTUB32865A

PDF File 74SSTUB32865A PDF File



Description
74SSTUB32865A www.
ti.
com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 •2 Member of the Texas Instruments Widebus+™ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2 RDIMMs • High driver strength for heavily loaded DIMMs • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line • Supports SSTL_18 Data Inputs • Differential Clock (CK and CK) Inputs • Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable and RESET Inputs • Checks Parity on DIMM-Independent Data Inputs • RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except PTYERR • Supports industrial temperature range (-40°C to 85°C) DESCRIPTION This 28-bit 1:2 configurable registered buffer is designed for 1.
7-V to 1.
9-V VCC operation.
One device per DIMM is required to drive up to stacked 18 SDRAM loads or two devices per DIMM are required to drive up to 36 stacked SDRAM loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are LVCMOS.
All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (PTYERR) output.
The 74SSTUB32865A operates from a differential clock (CK and CK).
Data are registered at the crossing of CK going high and CK going low.
The 74SSTUB32865A accepts a parity bit from the memory controller on the parity bit (PARIN) input, compares it with the data received on the DIMM-independent D-inputs (D0-D21) and indicates whether a parity error has occurred on the open-drain PTYERR pin (active low).
The convention is even parity, i.
e.
, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit.
To calculate parity, all DIMM-indepe...



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