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CD40106B

Texas Instruments
Part Number CD40106B
Manufacturer Texas Instruments
Description CMOS Hex Schmitt-Trigger Inverters
Published Feb 6, 2020
Detailed Description Product Folder Order Now Technical Documents Tools & Software Support & Community CD40106B SCHS097F – NOVEMBER 1998...
Datasheet PDF File CD40106B PDF File

CD40106B
CD40106B


Overview
Product Folder Order Now Technical Documents Tools & Software Support & Community CD40106B SCHS097F – NOVEMBER 1998 – REVISED MARCH 2017 CD40106B CMOS Hex Schmitt-Trigger Inverters 1 Features •1 Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.
9 V at VDD = 5 V – 2.
3 V at VDD = 10 V – 3.
5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at 20 V • Maximum Input Current Of 1 µA at 18 V Over Full Package Temperature Range: – 100 nA at 18 V and 25°C • Low VDD and VSS Current During Slow Input Ramp • 5-V, 10-V, and 15-V Parametric Ratings 2 Applications • Wave and Pulse Shapers • High-Noise-Environment Systems • Monostable Multivibrators • Astable Multivibrators 3 Description The CD40106B device consists of six Schmitt-Trigger inputs.
Each circuit functions as an inverter with Schmitt-Trigger input.
The trigger switches at different points for positive- and negative-going signals.
The difference between the positive-going voltage (VP) and the negative-going voltages (VN) is defined as hysteresis voltage (VH).
The CD40106B device is supplied in ceramic packaging (J) as well as standard packaging (D, N, NS, PW).
All CD40106B devices are rated for –55°C to +125°C ambient temperature operation.
Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD40106BF CDIP (14) 6.
92 mm x 19.
94 mm CD40106BE PDIP (14) 6.
30 mm x 19.
31 mm CD40106BM SOIC (14) 3.
90 mm x 8.
65 mm CD40106BNSR SO (14) 5.
30 mm x 10.
20 mm CD40106BPWR TSSOP (14) 4.
40 mm x 5.
00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram A 1 (3, 5, 9, 11, 13) G 2 (4, 6, 8, 10, 12) VDD VSS Copyright © 2017, Texas Instruments Incorporated All inputs protected by the protection network shown to the right 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critica...


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