Quad Static Shift Register - SMSC
Description
SR S01S-XXX
SR 5015-80 SR 5015-81 SR 5015-133
Quad Static Shift Register
FEATURES
D COPLAMOS® N Channel Silicon Gate Technology
D Variable Length-Single Mask Programmable-1 to 134 bits
D Directly TTL-compatible on all inputs, outputs, and clock
D Clear function D Operation guaranteed from DC to 1.
0 MHz
D Recirculate logic on-chip D Single +5.
0V power supply D Low clock input capacitance D 16 pin ceramic DIP Package D Pin for Pin replacement for AMI 82182.
83.
85
PIN CONFIGURATION
INPUT A RECASC
CLEAR INPUTS OUTPUTS
GND Vee OUTPUTC
OUTPUT A RID OUTPUTD INPUTD RECD NC INPUTC CLOCK
APPLICATIONS
D Memory Buffering D Unique Buffering Lengths D Terminals
BLOCK DIAGRAM
OUTPUT A
OUTPUT C
REC CONTROL ABC ~"""'--1
I
INPUT A "">--+--4
1----<: INPUT C
INPUT B
1------< RECIRC.
INPUT D
'--.
.
J--___- < REC.
CONTROL D
INPUT D
361
CLOCK CLEAR
General Description
The SMC SR 5015-XXX is a quad static shift register family fabricated using SMC's COPLAMOS@ N channel silicon gate process which provides a higher functional density and speed on a monolithic chip than conventional MaS technology.
The COPLAMOS® process provides high speed operation, low power dissipation, low clock input capacitance, and single +5 volt power supply operation.
These shift registers can be driven by either PL circuits or by MaS circuits and provide driving capability to MaS or PL circuits.
This device consists of four separate static shift registers with independent input and output terminals and logic for loading, recirculating or shifting information.
The SR 5015-80, SR 5015-81, and SR 5015-133 are respectively 80,81, and 133 bit quad shift registers.
The recirculate control pin is common for registers A, B, and C.
Register 0 has an independent recirculate control pin as well as a recirculate input pin.
A clear pin has been provided that will cause the shift register to be cleared when the pin is at Vee.
A single PL clock is required for operation.
The transfer of data into the register is ac...
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