HIGH-SPEED 3.3V STATIC RAM - IDT
Description
HIGH-SPEED 3.
3V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM
70V35/34S/L 70V25/24S/L
Features
◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location
◆ High-speed access IDT70V35 – Commercial: 15ns (max.
) – Industrial: 20ns IDT70V34 – Commercial: 15ns (max.
) IDT70V25 – Commercial: 15/35ns (max.
) – Industrial: 20/25ns IDT70V24 – Commercial: 15//35/55ns (max.
) – Industrial: 15/20ns
◆ Low-power operation – IDT70V35/34L Active: 415mW (typ.
) Standby: 660μW (typ.
)
Functional Block Diagram
R/WL UBL
– IDT70V25/24S
– IDT70V25/24L
Active: 400mW (typ.
)
Active: 380mW (typ.
)
Standby: 3.
3mW (typ.
)
Standby: 660μW (typ.
)
◆ Separate upper-byte and lower-byte control for multiplexed
bus compatibility
◆ IDT70V35/34 (IDT70V25/24) easily expands data bus width
to 36 bits (32 bits) or more using the Master/Slave select
when cascading more than one device
◆ M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆ BUSY and Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ LVTTL-compatible, single 3.
3V (±0.
3V) power supply
◆ Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24),
and 84-pin PLCC (IDT70V24)
◆ Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆ Green parts available, see ordering information
R/WR UBR
LBL CEL OEL
I/O9L-I/O17L(5)
I/O0L-I/O8L(4) BUSYL(2,3)
I/O Control
I/O Control
A12L(1) A0L
Address Decoder
13
CEL OEL
R/WL
MEMORY ARRAY
ARBITRATION INTERRUPT SEMAPHORE
LOGIC
13
SEML
NOTES:
INTL(3)
1.
A12 is a NC for IDT70V34 and for IDT70V24.
2.
(MASTER): BUSY is output; (SLAVE): BUSY is input.
3.
BUSY outputs and INT outputs are non-tri-stated push-pull.
4.
I/O0x - I/O7x for IDT70V25/24.
5.
I/O8x - I/O15x for IDT70V25/24.
©2019 Integrated Device Technology, Inc.
M/S
1
Address Decoder
CER OER R/WR
LBR CER OER
,
I/O9R-I/O17R(5)...
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