High-Speed CMOS Logic Dual 4-Input AND Gate - Texas Instruments
Description
Data sheet acquired from Harris Semiconductor SCHS131C
August 1997 - Revised September 2003
CD54HC21, CD74HC21, CD74HCT21
High-Speed CMOS Logic Dual 4-Input AND Gate
[ /Title (CD74H C21, CD74H CT21) /Subject (High Speed CMOS Logic Dual 4Input
Features
Description
• Buffered Inputs
•
Typical Propagation Delay: CL = 15pF, TA = 25oC
9ns
at
VCC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs .
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10 LSTTL Loads
- Bus Driver Outputs .
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15 LSTTL Loads
• Wide Operating Temperature Range .
.
.
-55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types
- 4.
5V to 5.
5V Operation
- Direct LSTTL Input Logic Compatibility, VIL= 0.
8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC21 and CD74HCT21 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits.
All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the standard LS logic family.
Ordering Information
PART NUMBER CD54HC21F3A CD74HC21E CD74HC21M CD74HC21MT CD74HC21M96 CD74HCT21E CD74HCT21M CD74HCT21MT CD74HCT21M96
TEMP.
RANGE (oC)
PACKAGE
-55 to 125
14 Ld CERDIP
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number.
The suffix 96 denotes tape and reel.
The suffix T denotes a small-quantity reel of 250.
Pinout
CD54HC21 (CERDIP) CD74HC21, CD74HCT21 (PDIP, SOIC) TOP VIEW
1A 1 1B 2 NC 3 1C 4 1D 5 1Y 6 GND 7
14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y
CAUTION: These devices are sensitive to electrostati...
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