Quad 2-input NAND gate - nexperia
Description
74AHC00; 74AHCT00
Quad 2-input NAND gate
Rev.
5 — 26 May 2020
Product data sheet
1.
General description
The 74AHC00; 74AHCT00 are quad 2-input NAND gates.
Inputs are overvoltage tolerant.
This feature allows the use of these devices as translators in mixed voltage environments.
2.
Features
• Wide supply voltage range from 2.
0 V to 5.
5 V • Input levels:
• For 74AHC00: CMOS level • For 74AHCT00: TTL level • Balanced propagation delays • All inputs have Schmitt-trigger actions • Overvoltage tolerant inputs to 5.
5 V • High noise immunity • CMOS low power dissipation • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V • Latch-up performance exceeds 100 mA per JESD 78 Class II Level A • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3.
Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC00D 74AHCT00D
-40 °C to +125 °C SO14
plastic small outline package; 14 leads; body width 3.
9 mm
SOT108-1
74AHC00PW 74AHCT00PW
-40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.
4 mm
74AHC00BQ 74AHCT00BQ
-40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm
SOT762-1
Nexperia
4.
Functional diagram
1 1A 2 1B
4 2A 5 2B
9 3A 10 3B
12 4A 13 4B
1Y 3 2Y 6 3Y 8 4Y 11
mna212
Fig.
1.
Logic symbol
1
2
&
3
4
5
&
6
9
10
&
8
12
13
&
11
mna246
Fig.
2.
IEC logic symbol
5.
Pinning information
74AHC00; 74AHCT00
Quad 2-input NAND gate
A Y
B
mna211
Fig.
3.
Logic diagram (one gate)
5.
1.
Pinning
1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7
14 VCC 13 4B
12 4A
00
11 4Y
10 3B
9 3A
8 3Y
001aac938
Fig.
4.
Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14)
5.
2.
Pin description
Table 2.
Pin description Symbol 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B...
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