• 2 – 1-167MHz Low-Power (LP) HCSL DIF pairs Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive p...
9DBU0231 PDF File
