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UT9Q512K32

Aeroflex Circuit Technology
Part Number UT9Q512K32
Manufacturer Aeroflex Circuit Technology
Description 16Megabit SRAM MCM
Published Oct 4, 2016
Detailed Description Standard Products QCOTSTM UT9Q512K32 16Megabit SRAM MCM Data Sheet March, 2009 FEATURES ‰ 25ns maximum (5 volt supply) ...
Datasheet PDF File UT9Q512K32 PDF File

UT9Q512K32
UT9Q512K32

Overview
Standard Products QCOTSTM UT9Q512K32 16Megabit SRAM MCM Data Sheet March, 2009 FEATURES ‰ 25ns maximum (5 volt supply) address access time ‰ Asynchronous operation for compatible with industry standard 512K x 8 SRAMs ‰ TTL compatible inputs and output levels, three-state bidirectional data bus ‰ Typical radiation performance - Total dose: 50krads - SEL Immune >80 MeV-cm2/mg - LETTH(0.
25) = >10 MeV-cm2/mg - Saturated Cross Section (cm2) per bit, 5.
0E-9 - <1E-8 errors/bit-day, Adams 90% geosynchronous heavy ion ‰ Packaging options: - 68-lead dual cavity ceramic quad flatpack (CQFP) (weight 7.
37 grams) ‰ Standard Microcircuit Drawing 5962-01511 - QML T and Q compliant part INTRODUCTION The QCOTSTM UT9Q512K32 Quantified Commercial Off-theShelf product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable.
Memory expansion is provided by an active LOW chip enable (En), an active LOW output enable (G), and three-state drivers.
This device has a power-down feature that reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking chip enable (En) input LOW and write enable (Wn) inputs LOW.
Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The input/output pins are placed in a high impedance state when the device is deselected (En HIGH), the outputs are disabled (G HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die.
A(18:0) G W3 E3 512K x 8 W2 E2 512K x 8 W1 E1 512K x 8 ...


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