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54HC190

National Semiconductor

Synchronous Decade Up/Down Counters - National Semiconductor


54HC190
54HC190

PDF File 54HC190 PDF File



Description
MM54HC190 MM74HC190 MM54HC191 MM74HC191 January 1988 MM54HC190 MM74HC190 Synchronous Decade Up Down Counters with Mode Control MM54HC191 MM74HC191 Synchronous Binary Up Down Counters with Mode Control General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power consumption of CMOS technology along with the speeds of low power Schottky TTL These circuits are synchronous reversible up down counters The MM54HC191 MM74HC191 are 4-bit binary counters and the MM54HC190 MM74HC190 are BCD counters Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously when so instructed by the steering logic This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters The outputs of the four master-slave flip-flops are triggered on a low-to-high level transition of the clock input if the enable input is low A high at the enable input inhibits counting The direction of the count is determined by the level of the down up input When low the counter counts up and when high it counts down These counters are fully programmable that is the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs The output will change independent of the level of the clock input This feature allows the counters to be used as modulo- N dividers by simply modifying the count length with the preset inputs Two outputs have been made available to perform the cascading function ripple clock and maximum minimum count The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condi...



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