DatasheetsPDF.com

NT5DS32M16CG

Nanya Techology

512Mb DDR SDRAM - Nanya Techology


NT5DS32M16CG
NT5DS32M16CG

PDF File NT5DS32M16CG PDF File



Description
NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features • DDR 512M bit, Die C, based on 90nm design rules • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2.
5, 3 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 7.
8µs Maximum Average Periodic Refresh Interval • 2.
5V (SSTL_2 compatible) I/O • VDD = VDDQ = 2.
6V ± 0.
1V (DDR400) • VDD = VDDQ = 2.
5V ± 0.
2V (DDR333) • RoHS compliance Description Die C of 512Mb SDRAM devices based using DDR interface.
They are all based on Nanya’s 90 nm design process.
The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
It is internally configured as a quad-bank DRAM.
The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 512Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes.
DQS is edgea...



Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)