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440BX AGPset Spread Spectrum Frequency Synthesizer

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PRELIMINARY
W150
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• 17 SDRAM outputs provide support for 4 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin 3
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F, 1:2
FS3 FS2 FS1 FS0
(MHz)
111 1
133.3
111 0
124
110 1
150
110 0
140
101 1
105
101 0
110
100 1
115
100 0
120
011 1
100
011 0
133.3
010 1
112
010 0
103
001 1
66.8
001 0
83.3
000 1
75
000 0
124
PCI_F, 0:5
(MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
X1
X2
CLK_STOP#
XTAL
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
I2C
Logic
Stop
Clock
Control
SDRAMIN
PLL2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC_F
IOAPIC0
VDDQ2
CPU_F
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:15
16 SDRAM_F
Pin Configuration[1]
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ2
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPU_F
51 CPU1
50 VDDQ2
49 CPU2
48 GND
47 CLK_STOP#
46 SDRAM_F
45 VDDQ3
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDQ3
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDDQ3
30 24MHz/FS0
29 48MHz/FS1
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 10, 2000, rev. *A
Cypress Semiconductor
Cypress Semiconductor



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