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440BX AGPset Spread Spectrum Frequency Synthesizer

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440BX AGPset Spread Spectrum
Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 150 MHz
• I2C™ interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew: ..............0.4 ns typ.
Table 1. Mode Input Table
Mode
0
1
Pin2
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS3 FS2 FS1 FS0
1 1 11
1 1 10
1 1 01
1 1 00
1 0 11
1 0 10
1 0 01
1 0 00
0 1 11
0 1 10
0 1 01
0 1 00
0 0 11
0 0 10
0 0 01
0 0 00
CPU_F, CPU1
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5 (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
Logic Block Diagram
Pin Configuration
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
CLK_STOP#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SDRAMIN
I2C
Logic
Stop
Clock
Control
PLL2
÷2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU1
CPU_F
VDDQ3
PCI_F/MODE
PCI1/FS3
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS0
24MHz/FS1
VDDQ3
SDRAM0:11
12
SDRAM_F
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 CLK_STOP#
40 SDRAM_F
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
Note:
1. Internal pull-up resistors should not be relied upon for setting
I/O pins HGH. Pin function with parentheses determined by
MODE pin resistor strapping. Unlike other I/O pins, input FS3
has an internal pull down resistor.
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999, rev. **
Cypress Semiconductor
Cypress Semiconductor



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