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TC511632FL-85 Datasheet

SILICON GATE CMOS PSEUDO STATIC RAM

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TC511632FL-85 pdf
Static RAM
TC511632FUFTL-70/8511 0
Notes:
1) Stress greater than those listed under "Maximum Ratings" may cause permanent damage to the device.
2) All voltages are referenced to GND.
3) 1000 depends on the cycle time.
4) 1000 depends on the output loading. Specified values are obtained with the outputs open.
5) An initial pause of 100llS with high CE is required after power-up before proper device operation is achieved.
6) AC measurements assume tT = 5ns.
7) Timing reference levels
Input Levels
Input Reference Levels
Output Reference Levels
V1H
V1L
= 2.6V
=0.6V
V1H = 2.4V
V1L =0.8V
VOH = 2.2V
VOL = 0.8V
INPUT
2.6V
O.6V
OUTPUT
INPUT REFERENCE
LEVEL
2.2V
OUTPUT REFERENCE
LEVEL
8) Measured with a load equivalent to 1 TIL load and 100pF.
9) tCHZ, tOHZ' tWHZ define the time at which the output achieves the open circuit condition and is not referenced to output
voltage levels.
10) For write cycles, the input data is latched at the earlier of WE or CE rising edge. Therefore, the input data must be valid
during the setup time (tosw or toscl and hold time (tOHW or tOHcl.
11) All address inputs,are latched at the falling edge of CEo Therefore, all the address inputs must be valid during tASC and tAHC '
12) The two refresh operations, auto refresh and self refresh, are defined by the RFSH pulse width under the condition CE ::: V1H.
Auto refresh : RFSH pulse width ~ tFAP (max.)
Self refresh : RFSH pulse width ~ tFAS (min.)
The timing parameter tFRs must be met for proper device operation under the following conditions:
• after self refresh
• if RFSH = ilL" after power-up
13) CE only refresh or auto refresh must begin within 15.61lS after self refreshing ends.
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
0-23
Toshiba
Toshiba



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