PCB Layout Recommendations
For the best performance, all traces should be as short
as possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effects that parasitic trace inductances
may have on normal and short-circuit operation (Figure
42). Using wide traces for IN, OUT, and GND pins helps
minimize parasitic electrical effects as well as the case-
to-ambient thermal impedance.
To minimize the interference between analog ground
(chip ground, pin 5) and power ground during load
current excursion, the ground terminal of the input and
output capacitors and the RSET resistor should be routed
directly to chip ground and away from power ground.
Improving Thermal Performance
Improper layout could result in higher junction
temperature and trigger thermal shutdown protection.
This is particularly significant for the FPF2702, where
the device operates in Constant Current Mode under
overload conditions. During fault conditions, the power
dissipation of the switch could exceed the maximum
absolute power dissipation.
The following techniques improve the thermal
performance of this family of devices. These techniques
are listed in order of the significance of their impact.
1. Thermal performance of the load switch can be
improved by connecting the Die Attach Pad (DAP) of
the MLP 3x3 package to the GND plane of the PCB.
2. Embedding two exposed through-hole vias into the
DAP provides a path for heat to transfer to the back
GND plane of the PCB. A drill size of round, 15 mils
(0.4 mm) with 1-ounce copper plating is
recommended for appropriate solder reflow. A
smaller-size hole prevents the solder from
penetrating into the via, resulting in device lift-up.
Similarly, a larger hole consumes excessive solder
and may result in voiding the DAP.
3. The IN, OUT, and GND pins dissipate most of the
heat generated during high-load current condition.
The layout suggested in Figure 42 and Figure 43 is
strongly recommended illustrating a proper layout
for devices in MLP 3x3 packages. IN, OUT, and
GND pins are connected to adequate copper so
that heat may be transferred as efficiently as
possible out of the device. The low-power FLAGB
and ON pins traces may be laid-out diagonally from
the device to maximize the area available to the
ground pad. Place the input and output capacitors
as close as possible to the device.
Figure 42. Proper Layout of Output and Ground
Copper Area (Top, SST, and AST Layers)
Figure 43. Proper Layout (Bottom and ASB Layers)
Figure 41. Two Through-Hole Open Vias
Embedded in the DAP
© 2010 Fairchild Semiconductor Corporation
FPF2700 / FPF2701 / FPF2702 • Rev. 1.0.3