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FPF1321 Datasheet
Dual-Input Single-Output Advanced Power Switch
Fairchild Semiconductor
Fairchild Semiconductor


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FPF1321 pdf
September 2013
FPF1320 / FPF1321
IntelliMAX™ Dual-Input Single-Output Advanced Power
Switch with True Reverse-Current Blocking
Features
DISO Load Switches
Input Supply Operating Range: 1.5 V ~ 5.5 V
RON 50 mat VIN=3.3 V Per Channel (Typical)
True Reverse-Current Blocking (TRCB)
Fixed Slew Rate Controlled 130 µs for < 1 µF COUT
ISW: 1.5 A Per Channel (Maximum)
Quick Discharge Feature on FPF1321
Logic CMOS IO Meets JESD76 Standard for GPIO
Interface and Related Power Supply Requirements
ESD Protected:
- Human Body Model: >6 kV
- Charged Device Model: >1.5 kV
- IEC 61000-4-2 Air Discharge: >15 kV
- IEC 61000-4-2 Contact Discharge: >8 kV
Applications
Smart phones / Tablet PCs
Portable Devices
Near Field Communication (NFC) Capable
SIM Card Power Supply
Description
The FPF1320/21 is a Dual-Input Single-Output (DISO)
load switch consisting of two sets of slew-rate
controlled, low on-resistance, P-channel MOSFET
switches and integrated analog features. The slew-rate-
controlled turn-on characteristic prevents inrush current
and the resulting excessive voltage droop on the power
rails. The input voltage range operates from 1.5 V to
5.5 V to align with the requirements of low-voltage
portable device power rails. FPF1320/21 performs
seamless power-source transitions between two input
power rails using the SEL pin with advanced break-
before-make operation.
FPF1320/21 has a TRCB function to block unwanted
reverse current from output to input during ON/OFF
states. The switch is controlled by logic inputs of the
SEL and EN pins, which are capable of interfacing
directly with low-voltage control signals (GPIO).
FPF1321 has 65 on-chip load resistor for output quick
discharge when EN is LOW.
FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP,
6-bump, with 0.5 mm pitch. FPF1321B is available in
1.0 mm x 1.5 mm WLCSP, 6-bump, 0.5 mm pitch with
backside laminate.
Ordering Information
Part Number
Top
Mark
Switch Per
Channel Channel (Typ.)
at 3.3 VIN
Reverse
Current
Blocking
Output Rise
Discharge Time (tR)
Package
FPF1320UCX QS DISO
FPF1321UCX QT DISO
50 m
50 m
Yes NA 130 µs 1.0 mm X 1.5 mm
Wafer-Level Chip-
Scale Package
Yes
65
130 µs
(WLCSP) 6-Bumps,
0.5 mm Pitch
FPF1321BUCX QT DISO
50 m
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
1.0 mm X 1.5 mm
Wafer-Level Chip-
Yes
65
130 µs
Scale Package
(WLCSP) 6-Bumps,
0.5 mm Pitch with
Backside Laminate
www.fairchildsemi.com

FPF1321 Datasheet PDF



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