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FPF1320 Datasheet

Dual-Input Single-Output Advanced Power Switch

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Operation and Application Description
The FPF1320 and FPF1321 are dual-input single-output
power multiplexer switches with controlled turn-on and
seamless power source transition. The core is a 50 m
P-channel MOSFET and controller capable of
functioning over a wide input operating range of 1.5 V to
5.5 V per channel. The EN and SEL pins are active-
HIGH, GPIO/CMOS-compatible input. They control the
state of the switch and input power source selection,
respectively. TRCB functionality blocks unwanted
reverse current during both ON and OFF states when
higher VOUT than VINA or VINB is applied. FPF1321 has a
65 output discharge path during off.
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor; a capacitor must be placed
between the VINA or VINB pins to the GND pin. At least
1 µF ceramic capacitor, CIN, placed close to the pins, is
usually sufficient. Higher-value CIN can be used to
reduce more the voltage drop.
Inrush Current
Inrush current occurs when the device is turned on.
Inrush current is dependent on output capacitance and
slew rate control capability, as expressed by:
COUT: Output capacitance;
tR: Slew rate or rise time at VOUT;
VIN: Input voltage, VINA or VINB;
VINITIAL: Initial voltage at COUT, usually GND; and
ILOAD: Load current.
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130 µs of slew rate capability under
3.3 VIN at 1 µF of COUT and 150 of RL so inrush
current and input voltage drop can be minimized.
Power Source Selection
Input power source selection can be controlled by the
SEL pin. When SEL is LOW, output is powered from
VINA while SEL is HIGH, VINB is powering output. The
SEL signal is ignored during device OFF.
Output Voltage Drop during Transition
Output voltage drop usually occurs during input power
source transition period from low voltage to high
voltage. The drop is highly dependent on output
capacitance and load current.
FPF1320/1 adopts an advanced break-before-make
control, which can result in minimized output voltage
drop during the transition time.
Output Capacitor
Capacitor COUT of at least 1 µF is highly recommended
between the VOUT and GND pins to achieve minimized
output voltage drop during input power source transition.
This capacitor also prevents parasitic board inductance.
True Reverse-Current Blocking
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switch is on or off.
Board Layout
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
normal and short-circuit operation. Wide traces or large
copper planes for power pins (VINA, VINB, VOUT and
GND) minimize the parasitic electrical effects and the
thermal impedance.
© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.2
Fairchild Semiconductor
Fairchild Semiconductor

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