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(Datasheet) FDMS3624S

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Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 30 A
8
6
4
2
VDD = 10 V
VDD = 13 V
VDD = 15 V
0
0 10 20 30 40 50 60
Qg, GATE CHARGE (nC)
Figure 20. Gate Charge Characteristics
10000
1000
Ciss
Coss
100
f = 1 MHz
VGS = 0 V
Crss
10
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 21. Capacitance vs Drain
to Source Voltage
100
TJ = 25 oC
10 TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)
1000
Figure 22. Unclamped Inductive
Switching Capability
150
120
VGS = 10 V
90
VGS = 4.5 V
60
Limited by Package
30 RθJC = 2.2 oC/W
0
25 50 75 100 125 150
TC, CASE TEMPERATURE (oC)
Figure 23. Maximum Continuous Drain
Current vs Case Temperature
200
100 100 μs
10
1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 120 oC/W
TA = 25 oC
0.01
0.01
0.1
1
10
VDS, DRAIN to SOURCE VOLTAGE (V)
10 ms
100 ms
1s
10s
DC
100
Figure 24. Forward Bias Safe
Operating Area
3000
1000
100
SINGLE PULSE
RθJA = 120 oC/W
10
1
0.5
10-4 10-3 10-2 10-1
1
10 100 1000
t, PULSE WIDTH (sec)
Figure 25. Single Pulse Maximum Power
Dissipation
©2011 Fairchild Semiconductor Corporation
FDMS3624S Rev.C2
8
www.fairchildsemi.com
Fairchild Semiconductor
Fairchild Semiconductor


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