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FDMC8200S Datasheet

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FDMC8200S pdf
March 2011
FDMC8200S
Dual N-Channel PowerTrench® MOSFET
30 V, 10 mΩ, 20 mΩ
Features
Q1: N-Channel
„ Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 6 A
„ Max rDS(on) = 32 mΩ at VGS = 4.5 V, ID = 5 A
Q2: N-Channel
„ Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 8.5 A
„ Max rDS(on) = 13.5 mΩ at VGS = 4.5 V, ID = 7.2 A
„ RoHS Compliant
General Description
This device includes two specialized N-Channel MOSFETs in a
due power33(3mm X 3mm MLP) package. The switch node has
been internally connected to enable easy placement and routing
of synchronous buck converters. The control MOSFET (Q1) and
synchronous MOSFET (Q2) have been designed to provide
optimal power efficiency.
Applications
„ Mobile Computing
„ Mobile Internet Devices
„ General Purpose Point of Load
Pin 1
Bottom
D1
D1
D1
G1
D1
D2/S1
S2
S2
S2
G2
Bottom
VIN VIN
GHSVIN
VIN
SWITCH
NODE
GND
GND
GND
GLS
5 Q2
6
7
8
4
3
2
1
Q1
Power33
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
TC = 25 °C
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
TA = 25°C
Power Dissipation for Single Operation
TA = 25°C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
(Note 3)
Q1 Q2
30 30
±20 ±20
18 13
23 46
6 1a 8.5 1b
40 27
12
1.9 1a
0.7 1c
32
2.5 1b
1.0 1d
-55 to +150
Units
V
V
A
W
°C
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
65 1a
180 1c
7.5
50 1b
125 1d
4.2
°C/W
Device Marking
FDMC8200S
Device
FDMC8200S
Package
Power 33
Reel Size
13”
Tape Width
12 mm
Quantity
3000 units
©2011 Fairchild Semiconductor Corporation
FDMC8200S Rev.C4
1
www.fairchildsemi.com
Fairchild Semiconductor
Fairchild Semiconductor


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