Revised February 2000
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
must not be allowed to change while the clock is HIGH.
The data is transferred to the outputs on the falling edge of
the clock pulse. A LOW logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Order Number Package Number
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
PR CLR CLK J
(Note 1) (Note 1)
L L Q0 Q0
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
= Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q0 = The output logic level before the indicated input conditions were
Toggle = Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.
© 2000 Fairchild Semiconductor Corporation DS006528