Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
• Digital Visual Interface (DVI) Transmitter up to 165M The CH7303 is a Display Controller device which accepts a
• DVI low jitter PLL
• DVI hot plug detection
• Analog YPrPb outputs for HDTV
• HDTV support for 480p, 576p, 720p, 1080i and 1080p
• MacrovisionTM copy protection support for HDTV
digital graphics input signal, and encodes and transmits data
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
up to UXGA. The device accepts data over one 15-bit wide
variable voltage data port which supports 9 different data
• Programmable digital input interface supporting RGB formats including RGB and YCrCb.
(15, 16, 24 or 30 bit) and YCrCb input data formats
• Can output either RGB or YPrPb
• TV / Monitor connection detect
• Programmable power management
• Three 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
• Offered in a 64-pin LQFP package
• Backward pin compatible with CH7301 or CH7009/11
• Support three additional 15 bit multiplexed RGB Input
In addition to DVI encoder modes, bypass modes are included
which perform color space conversion to HDTV standards
and generate and insert HDTV sync signals, or output VGA
Data Format (IDF 6,7.8)
style analog RGB for use as a CRT DAC.
† Patent number 5,781,241
¥ Patent number 5,914,753
Note: Other names and brands may be claimed as property by others.
24 Sync Decode
/ TLC, TLC*
/ TDC0, TDC0*
Figure 1: Functional Block Diagram
209-0000-031 Rev. 0.4, 8/26/2002