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ATmega1284P Datasheet

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9. System clock and clock options
9.1 Clock systems and their distribution
Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be
halted by using different sleep modes, as described in ”Power management and sleep modes” on page 42. The
clock systems are detailed below.
Figure 9-1.
Clock distribution.
Asynchronous
Timer/Counter
General I/O
Modules
ADC
CPU Core
RAM
Flash and
EEPROM
clkI/O
clkASY
clkADC
AVR Clock
Control Unit
clkCPU
clkFLASH
Reset Logic
Watchdog Timer
Source clock
System Clock
Prescaler
Clock
Multiplexer
Watchdog clock
Watchdog
Oscillator
Timer/Counter
Oscillator
External Clock
Crystal
Oscillator
Low-frequency
Crystal Oscillator
Calibrated RC
Oscillator
9.1.1
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
9.1.2
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous
logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition
detection in the USI module is carried out asynchronously when clkI/O is halted, TWI address recognition in all
sleep modes.
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET]
Atmel-8272G-AVR-01/2015
30
ATMEL Corporation
ATMEL Corporation



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