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Figure 7-5.
The Parallel Instruction Fetches and Instruction Executions.
T1 T2
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 7-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-6. Single Cycle ALU operation.
T2 T3
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
7.7 Reset and interrupt handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each
have a separate program vector in the program memory space. All interrupts are assigned individual enable bits
which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to
enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section
”Memory programming” on page 287 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in ”Interrupts” on page 61. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot
Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 61
for more information. The Reset Vector can also be moved to the start of the Boot Flash section by
programming the BOOTRST Fuse, see ”Memory programming” on page 287.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P [DATASHEET]
ATMEL Corporation
ATMEL Corporation

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