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ATmega1284 Datasheet

8-bit AVR Microcontrollers

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8. AVR CPU Core
8.1.
Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations, control peripherals, and handle interrupts.
Figure 8-1. Block Diagram of the AVR Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R19 R18
R17 R16
R15 R14
R13 R12
R11 R10
R9 R8
R7 R6
R5 R4
R3 R2
R1 R0
Program
counter
Flash program
memory
Instruction
register
Instruction
decode
Stack
pointer
Status
register
ALU
Data memory
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a
single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock
cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU
operation, two operands are output from the Register File, the operation is executed, and the result is
stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space
addressing – enabling efficient address calculations. One of the these address pointers can also be used
as an address pointer for look up tables in Flash program memory. These added function registers are
the 16-bit X-, Y-, and Z-register, described later in this section.
Atmel ATmega1284 [DATASHEET]
Atmel-42718B-ATmega1284_Datasheet_Complete-08/2016
19
ATMEL
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