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ATMEGA1281V Datasheet

8-bit Atmel Microcontroller

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Figure 8-2.
Data Memory Map
Address (HEX)
0 - 1F
20 - 5F
60 - 1FF
200
21FF
2200
32 Registers
64 I/O Registers
416 External I/O Registers
Internal SRAM
(8192 × 8)
External SRAM
(0 - 64K × 8)
FFFF
8.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clkCPU cycles as described in Figure 8-3.
Figure 8-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
Memory Access Instruction
Next Instruction
8.3 EEPROM Data Memory
The ATmega640/1280/1281/2560/2561 contains 4Kbytes of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see “Serial Downloading”
on page 338, “Programming via the JTAG Interface” on page 342, and “Programming the EEPROM” on page 333
respectively.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
22
ATMEL
ATMEL


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