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ATMEGA1281 Datasheet
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8.4 I/O Memory
8.4.1
The I/O space definition of the ATmega640/1280/1281/2560/2561 is shown in “Register Summary” on page 399.
All ATmega640/1280/1281/2560/2561 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose
working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible
using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS
and SBIC instructions. Refer to the “Instruction Set Summary” on page 404 for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as
data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such
Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
General Purpose I/O Registers
The ATmega640/1280/1281/2560/2561 contains three General Purpose I/O Registers. These registers can be
used for storing any information, and they are particularly useful for storing global variables and Status Flags. Gen-
eral Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI,
SBIS, and SBIC instructions. See “Register Description” on page 34.
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
26

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