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ATMEGA1280V Datasheet

8-bit Atmel Microcontroller

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ATMEGA1280V datasheet pdf
Figure 9-4. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)
T1 T2 T3 T4
System Clock (CLKCPU)
ALE
A15:8 Prev. addr.
Address
DA7:0 Prev. data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. data
Address
Data
DA7:0 (XMBK = 1) Prev. data
Address
Data
RD
T5
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sec-
tor).
The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).
Figure 9-5. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)
T1
T2
T3 T4
T5
System Clock (CLKCPU)
T6
ALE
A15:8 Prev. addr.
Address
DA7:0 Prev. data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. data
Address
Data
DA7:0 (XMBK = 1) Prev. data
Address
Data
RD
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sec-
tor).
The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
30
ATMEL
ATMEL



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