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7.4.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
Bit
0x3F (0x5F)
Read/Write
Initial Value
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the inter-
rupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the “Instruction Set Summary” on
page 404.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the oper-
ated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic.
See the “Instruction Set Summary” on page 404 for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Summary” on page 404 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Sum-
mary” on page 404 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Sum-
mary” on page 404 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Summary” on
page 404 for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Summary” on page
404 for detailed information.
7.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor-
mance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
2549Q–AVR–02/2014
13

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