Home >> ATMEGA128 Search >> ATMEL Corporation ATMEGA128 Datasheet

ATMEGA128 Datasheet

8-bit Atmel Microcontroller

No Preview Available !

ATMEGA128 pdf
ATmega128
Data Memory Access
Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.
Figure 10. On-chip Data SRAM Access Cycles
T1 T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
Memory access instruction
Next instruction
EEPROM Data
Memory
The Atmel® AVR®ATmega128 contains 4Kbytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
“Memory Programming” on page 286 contains a detailed description on EEPROM programming
in SPI, JTAG, or Parallel Programming mode
EEPROM Read/Write
Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-
ing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
EEPROM Address
Register – EEARH and
EEARL
Bit
Read/Write
Initial Value
15
EEAR7
7
R
R/W
0
X
14
EEAR6
6
R
R/W
0
X
13
EEAR5
5
R
R/W
0
X
12
EEAR4
4
R
R/W
0
X
11
EEAR11
EEAR3
3
R/W
R/W
X
X
10
EEAR10
EEAR2
2
R/W
R/W
X
X
9
EEAR9
EEAR1
1
R/W
R/W
X
X
8
EEAR8
EEAR0
0
R/W
R/W
X
X
EEARH
EEARL
• Bits 15..12 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
2467X–AVR–06/11
20
ATMEL Corporation
ATMEL Corporation



   PDF Click to Download PDF File

   PDF View for Mobile





Related Start with ATMEGA12*

[ ATMEGA128 ATMEL Corporation ]     [ ATMEGA1280 ATMEL Corporation ]     [ ATMEGA1280V ATMEL ]     [ ATMEGA1281 ATMEL Corporation ]     [ ATMEGA1281V ATMEL ]     [ ATMEGA1284 ATMEL Corporation ]     [ ATMEGA1284 ATMEL ]     [ ATMEGA1284P ATMEL Corporation ]     [ ATMEGA1284P ATMEL ]     [ ATMEGA1284RFR2 ATMEL ]     [ ATMEGA128A ATMEL Corporation ]     [ ATMEGA128L ATMEL Corporation ]     [ ATMEGA128RFA1 Atmel Corporation ]     [ ATMEGA128RFR2 ATMEL ]     [ ATMEGA103 ATMEL Corporation ]     [ ATMEGA103L ATMEL Corporation ]     [ ATMEGA128 ATMEL Corporation ]     [ ATMEGA1280 ATMEL Corporation ]     [ ATMEGA1280V ATMEL ]     [ ATMEGA1281 ATMEL Corporation ]     [ ATMEGA1281V ATMEL ]     [ ATMEGA1284 ATMEL Corporation ]     [ ATMEGA1284 ATMEL ]     [ ATMEGA1284P ATMEL Corporation ]    


Searches related to ATMEGA128 part

Find Chips CBC RS online RUTRONIK 24
Component Distributors NexGen Digital Richardson RFPD ICC
Beyond Components NAC PEI-Genesis Powell Electronics
TME Ameya 360 Power & Signal Datasheets360
Freelance Electronics Sager Electronics Terminals & Connectors TTI

0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z
@ 2014 :: DatasheetsPDF.com :: Semiconductors Datasheet Search & Download Site